This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes. It can support Slave side. Each lane supports 2.5Gbps in High-Speed mode and 10Mbps/lane in Low-Power escape mode. The target applications are CSI-2 and DSI physical layers.