Logicatoms offer the High performance,high quality, fully verified , reliable Memory Controller IP core for GDDR6 SGRAM devices.
Please Note the IP core contains "Controller" only and the PHY is not included.
-Memory controller for GDDR6 memory devices compliant to JEDEC Specification.
-The Memory Controller comes in FPGA and ASIC verisons.
-Ready to integrate with PHY.
-Floor-plan,Power,Frequency and P&R aware Design.
-Support for all kind of system memory bus interface and protocols.
-Ssupport for all kind of system CSR bus interface and protocols.
-High throughput architecture with accurate refresh and interface training + calibration functions for reliability.
-Refresh Per Bank and Per 2 Bank feature support.
- -Fully loaded memory controller supporting every features of the GDDR6 standard including optional features.
- -support for both 2 channel and pseudo channel configurations.
- -reliability and high throughput oriented micro architecture.
- -low power system power management interface to dynamically issue self-refresh and power down commands.
- -scalable and portable PHY front-end block to support multiple devices sharing same command/address bus.
- -support refresh all bank and refresh per bank.
- -Request ordering based on address mapping, write combining, read over write, starvation counter based scheduling.
- -coverage driven + self checking test-bench.
- -portable for both multi core as well as single core processor platforms.
- Fully Customizable design.
- Freedom to optimize the design for unique implementations that would require the modification of the source on a per-use basis.
- Simple Licencing scheme free of financial, temporal, and contractual overheads.
- Fully compliant to the industry standard.
- Verification sign-off based on exhaustive stimulus with self checking test-bench.
- Source code with well documented Comments.
- Reference Manuals, Integration guide and Debugging Manual.
- Free of cost Memory controller wrapper to integrate with PHY.
- Pre and post silicon technical support in bring-up and debug.
- Dedicated support in PHY integration and verification.
- Synthesizable RTL design in Verilog.
- Testbench + test suite.
- Technical Refrence manual.
- IP core Integration guide.
- Graphics Cards.
- Gaming Consoles.
- HPC/Super Computing.
- Coin Mining.
- cryptocurrency systems.
- High Bandwidth Parallel Computing Co-processors.
- automotive ICs,
- cloud computing / data center class server SOCs.