32-bit RISC Processor To Deliver High Performance In Low-Cost Microcontroller Applications
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FlexNoC Resilience Package IP
For complex SoCs in advanced process nodes, CPU duplication and memory protection logic are no longer sufficient to address all the metrics required to meet the more stringent ISO 26262 ASIL and IEC 61508 SIL levels.
In addition to providing functional-safety compliant IP, Arteris is working closely with YOGITECH S.p.A. to create a set of deliverables which can be used as a starting point in the preparation of ISO 26262 work products.
Implementing functional safety and data protection features in hardware is easier and less risky than software-only implementations.
In addition to providing functional-safety compliant IP, Arteris is working closely with YOGITECH S.p.A. to create a set of deliverables which can be used as a starting point in the preparation of ISO 26262 work products.
Implementing functional safety and data protection features in hardware is easier and less risky than software-only implementations.
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Block Diagram of the FlexNoC Resilience Package IP
