eUSB2 PHY for TSMC N5
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was originally defined in the USB 1.0 specification from 1994 and is required for backwards compatibility. The eUSB2 specification defines new, lower voltage USB signaling that is used for low power chip-to-chip communication. eUSB2 repeater converts between standard USB 2.0 and eUSB2 signaling levels, allowing legacy USB 2.0 devices to connect to a system-on-chip (SoC) with eUSB2 PHY.
DesignWare USB IP is built on years of customer success with Synopsys’ silicon-proven USB PHY product line, which has been ported to over 100 process nodes ranging from 180nm to 5nm. When combined with the DesignWare Host, Device or Dual Role digital controllers and verified using Synopsys’ verification IP, the DesignWare eUSB2 IP delivers a complete USB 2.0 solution for advanced SoC designs
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Video Demo of the eUSB2 PHY for TSMC N5
USB 2.0 has been around for over 20 years and is the world's most popular wired interconnect standard. Join Morten Christiansen and Gervais Fong as they discuss how the new eUSB2 standard enables USB 2.0 connectivity for SoCs in the most advanced process nodes.
USB IP
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- USB 3.0 femtoPHY, Type-C in TSMC (28nm, 16nm, 12nm)
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- USB 3.1 PHY (10G/5G) in TSMC (16nm, 12nm, 7nm, 5nm)
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- Complete USB Type-C Power Delivery PHY, RTL, and Software