MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
Ethernet TSN MAC 10M/100M/1G/2.5G
The TSN MAC enables deterministic low latency and guaranteed jitter for time sensitive applications. The TSN MAC allows flexibility in selecting a subset of standards depending on your application from industrial to automotive.
The feature rich MAC core is a low latency cut-through implementation, while keeping size at a minimum. The core is fully configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC Core has a standard GMII interface on the PHY side, with MII and RGMII being optional.
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Block Diagram of the Ethernet TSN MAC 10M/100M/1G/2.5G
