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eDP v1.5a RX PHY (14nm)
	The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is commonly used for connecting a multi-protocol interface to a host processor.
 
		
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Block Diagram of the eDP v1.5a RX PHY (14nm)
	Display IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
 - VESA DSC (Display Stream Compression) 1.2b Video Decoder
 - ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
 - VDC-M (VESA Display Compression-M) Encoder
 - VDC-M (VESA Display Compression-M) Decoder
 - VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
 



