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DVB-RCS2 Turbo Decoder and Encoder IP Core
On the transmitter side, the turbo-phi encoder architecture is based on a parallel concatenation of two double-binary Recursive Systematic Convolutional (RSC) encoders, fed by blocks of K bits (N=K/2). It is a 16-state double-binary turbo encoder.
On the receiver side, the turbo decoder engine is built using two functioning soft-in/soft-out modules (SISO). The outputs of one SISO, after applying the scaling and interleaving are used by its dual SISO in the next half iteration.
Both the turbo encoder and decoder are fully compliant with the DVB-RCS2, supporting all its code rates and block sizes.
On the receiver side, the turbo decoder engine is built using two functioning soft-in/soft-out modules (SISO). The outputs of one SISO, after applying the scaling and interleaving are used by its dual SISO in the next half iteration.
Both the turbo encoder and decoder are fully compliant with the DVB-RCS2, supporting all its code rates and block sizes.
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