Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
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Dual Port SRAM Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density Dual Port (2RW) SRAM memory compiler.
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