Dual Parallel FFT

特色

• Fastest most power efficient architecture optimized for 128 to 4096 points FFTs
• Optimized Butterflies/Dragonflies, reductions from constant twiddle factors reduces logic
• No pipeline limit, fully asynchronous to maximum pipeline stages
• upto 32 points in/out per clock cycle, ultra high performance, 12.5 GSPS+ possible in FPGA
• lengths up to 4096 points practical in FPGAs