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DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interfaces, with resulting output Status on Status Stream, AXI4-Stream Interfaces.
Digital Blocks offers two version releases of the DB-DMAC-MC2-CS-MM2S-S2MM:
• High AXI bandwidth throughput version with internal control plane that keeps the data interfaces transferring data at the full AXI Interface capabilities.
• Nominal bandwidth throughput version requiring less control plane VLSI resources at a lower licensing cost
Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interfaces, with resulting output Status on Status Stream, AXI4-Stream Interfaces.
Digital Blocks offers two version releases of the DB-DMAC-MC2-CS-MM2S-S2MM:
• High AXI bandwidth throughput version with internal control plane that keeps the data interfaces transferring data at the full AXI Interface capabilities.
• Nominal bandwidth throughput version requiring less control plane VLSI resources at a lower licensing cost
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Block Diagram of the DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
AXI4-Stream Interface IP
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