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DMA AXI4-Stream Interface to AXI Memory Map Address Space
Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Memory Map address, and signals a DMA Controller to read the data by way of a AXI4 Slave Memory Map read channel.
The Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE IP Core works with Digital Blocks DMA Controller (i.e. the DB-DMAC-MC-AXI Verilog RTL IP Core) to transfer data from an AXI4-Stream peripheral or AXI4-Stream Network Interface to either memory or another peripheral.
The Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE IP Core works with Digital Blocks DMA Controller (i.e. the DB-DMAC-MC-AXI Verilog RTL IP Core) to transfer data from an AXI4-Stream peripheral or AXI4-Stream Network Interface to either memory or another peripheral.
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AXI4-Stream Interface IP
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- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface
- Receives video data from Flir's Lepton IR-sensors, Video over SPI (VoSPI)
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List