MW_ASI/SMPTE_SERDES cores implements related standards, by means of a precise and robust design, to inexpensive devices, (from Spartan3 up to 7Series families) using reduced FPGA resources.
This implies, at system level, two major benefits:
– No external deserializer devices are required
– Several instances of the core can be mapped in the same low-cost FPGA
MW_ASI/SMPTE_SERDES_RX performs three major tasks:
– Recovery and resampling serial data
– Framing data in the correct word boundary
– Decoding the 8B/10B encoded word
– TS flow delineation and synchronization
– TS flow adapting to user clock
MW_ASI/SMPTE_SERDES_TX adapts TS flow from yser clock to transmission clock, encodes words in 8B/10B format and serializes the data for transmission.
Clock infrastructures (PLLs, DCMs, BUFGs) are common to all core instances.
- Compatible with DVB standard
- 310/270 Mbit Asynchronous
- Robust Jitter tolerance
- Polarity Insensitive
- 8B/10B coding
- TS framing
- Rate adaptation
- ASI received clock recovery (for “seamless” applications)
- Rx Clock Jitter compensation (up to 0.6 U.I.)