You are here:
Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm 80GC,LP_EMF
Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 3.1 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
查看 Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm 80GC,LP_EMF 详细介绍：
- 查看 Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm 80GC,LP_EMF 完整数据手册
- 联系 Digital Delay Locked Loop (133MHz – 333MHz) - TSMC 80nm 80GC,LP_EMF 供应商
interface IP IP
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 6.1 Controller
- PCIe 5.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface