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Decision tree evaluation core using serial architecture
So_ip_edt_un core can be used to implement the decision tree with the previously defined structure directly in hardware. It uses a simple sequential architecture that allows the smallest possible DT hardware implementation.
So_ip_edt_un core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_edt_un design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_edt_un core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
So_ip_edt_un core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_edt_un design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_edt_un core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
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