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DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
This DDR (Double Data Rate) PHY IP supports DRAM type DDR3L/DDR4/ LPDDR4, this PHY provides low latency, and enables up to 1866Mbps throughput. The DDR IP is compliant with the latest JEDEC standards and is silicon proven. The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market.
The DDR PHY is interface between DDR controller and SDRAM. The DDR controller is used to control DRAM devices as well as to access the data stored on these devices. Provide multiple AXI interface for AXI master and support DFI standard for DDR PHY to support DDR3L/4, LPDDR4 date rate 1600~3200 Mbps, X8/X16, four ranks, Write leveling, Data training, low power mode and standby mode. The DDR (Double Data Rate) PHY is used to control DRAM devices, to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and LPDDR4.
The DDR PHY is interface between DDR controller and SDRAM. The DDR controller is used to control DRAM devices as well as to access the data stored on these devices. Provide multiple AXI interface for AXI master and support DFI standard for DDR PHY to support DDR3L/4, LPDDR4 date rate 1600~3200 Mbps, X8/X16, four ranks, Write leveling, Data training, low power mode and standby mode. The DDR (Double Data Rate) PHY is used to control DRAM devices, to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and LPDDR4.
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Block Diagram of the DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
