8kx8 Bits OTP (One-Time Programmable) IP, X-FA- 0.18μm XH018 Modular Mixed Signal Process
You are here:
DDR3/3L/DDR4/LPDDR4 PHY
The DDR3, DDR3L, DDR4, and LPDDR4 Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected to a third-party DFI-compliant DDR3, DDR3L, DDR4, or LPDDR4 memory controller. Depending on the type of package and PCB layout, DDR3 and DDR3L can operate at speeds up to 2,133 Mbps, while DDR4 and LPDDR4 can operate at speeds up to 2,667 Mbps in wirebond packages such as QFP or QFN.
Optimized for low power, low latency, high performance, and small area, the InPsytech DDR/LPDDR combo PHY is provided as a hard macro, primarily delivered in GDSII format. Supporting the PHY macro is the RTL-based Calibration Accessories for PHY (CAP), which manages control features such as training, read/write leveling, skew controls, and PVT compensation, while also supporting manufacturing testing. The CAP includes an optional MCU for executing hardware-assisted, firmware-based training algorithms.
For further information, please contact an InPsytech sales representative at sales@inpsytech.com for details.
Optimized for low power, low latency, high performance, and small area, the InPsytech DDR/LPDDR combo PHY is provided as a hard macro, primarily delivered in GDSII format. Supporting the PHY macro is the RTL-based Calibration Accessories for PHY (CAP), which manages control features such as training, read/write leveling, skew controls, and PVT compensation, while also supporting manufacturing testing. The CAP includes an optional MCU for executing hardware-assisted, firmware-based training algorithms.
For further information, please contact an InPsytech sales representative at sales@inpsytech.com for details.
查看 DDR3/3L/DDR4/LPDDR4 PHY 详细介绍：
- 查看 DDR3/3L/DDR4/LPDDR4 PHY 完整数据手册
- 联系 DDR3/3L/DDR4/LPDDR4 PHY 供应商
Block Diagram of the DDR3/3L/DDR4/LPDDR4 PHY
