You are here:
DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process
It is a UMC 0.13um HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage.
查看 DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process 详细介绍：
- 查看 DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process 完整数据手册
- 联系 DDR DLL IP, Input: 400MHz - 533MHz, Output: 200MHz - 266MHz (13.5% - 36.6% Delay), UMC 0.13um HS/FSG process 供应商
PLL/DLL IP
- Programmable DLL, fully digital PLL - TSMC 28nm 28HP (CLN28HP)
- Programmable DLL, fully digital PLL - TSMC 40nm 40G (CLN40G)
- Programmable DLL, fully digital PLL - TSMC 40nm 40LP (CLN40lp)
- Fully Digital Glitch Free PLL TSMC HPC+28nm - 200-2000 MHz
- High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional-N PLL for Performance Computing in GlobalFoundries 22FDX