This PLL is designed for audio clock generation. It can support 8.192MHz/10MHz/12MHz/12.288MHz/13MHz/13.5MHz/19.2MHz/21.25MHz/24MHz/26MHz/38.85MHz as reference, which is either a crystal or an input clock from other sources,.
This IP supports 256*fs and 128*fs clock output, wherein fs is the audio system’s sample rate of 8kHz/11kHz/12kHz/16kHz/22kHz/24kHz/32kHz/44.1kHz/48kHz/96kHz. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.
- Process: CSMC 0.13um Logic 1P8M 1.2V/3.3V CMOS process
- Supply voltage: 3.3v +/-10%; 1.2v+/-10%
- Output duty cycle: 45~55%
- Current: <1mA
- Operating junction temperature: -40~125°C