16bit 5Gsps silicon proven High performance Current Steering DAC IP Core
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Controller Area Networks, CAN 2.0B Bus Controller IP Core
CAN is part of HCL’s IP offerings and supports Version 2.0, PART B specification released by Bosch. This IP supports standard FIFO interface at application side and standard interface that would get connected to CAN Transceiver. It offers a simple register interface for communication with host. This register interface can be customized quickly if needed, for other leading industry standard bus interface to host such as Avalon, AXI4 – Lite, AHB, and APB. This IP is efficient and functionally verified and well tested design for the CAN (Version 2.0, PART B) and can be immediately used in SoC designs in need of the CAN Interface.
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Block Diagram of the Controller Area Networks, CAN 2.0B Bus Controller IP Core
