The Bk3 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and is offered in versions with either 16 or 32 general-purpose registers.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip Bk cores, it is possible to create custom instructions using Codasip Studio to extend the Bk3 and to generate corresponding hardware and software development kits.
- 32-bit RISC-V core
- Available in three versions:
- Either 16 [RV32E] or 32 [RV32I] general purpose registers
- Either small serial or fully parallel multiplier
- 3-stage pipeline
- Dynamic branch predictor
- RISC-V mode support:
- Internal interrupt controller
- Optional FPU
- Optional instruction and data tightly coupled memories (TCM)
- Optional 8 or 16 PMP regions
- Optional L1 data and instruction caches
- On-chip debugger
- JTAG and RISC-V Debug module
- Wide choice of configuration options.
- Ability to create custom RISC-V extensions to optimise performance
- Efficient architectural exploration of custom extensions with Studio
- Automatic HDK and SDK generation from Studio
- Rigorous verification of modified Bk3 core using UVM
- Human-readable and structured RTL in either:
- System Verilog
- Hardware development kit (HDK)
- Synthesis scripts
- Simulation testbenches
- Debug support
- Software development kit (SDK)
- LLVM C-compiler
- Instruction-accurate simulator
- Cycle-accurate simulator
- Option for extending Bk3
- CodAL model for Codasip Studio
- The Bk3 is aimed at low- to mid-range embedded applications such as IoT, always on sensors, wireless connectivity, audio, motor control and display control.
Block Diagram of the Compact RISC-V Processor - 32 bit, 3-stage