Linear Li-Ion Battery Charger - ±1% Accuracy (4.2V) / Up to 1.1A Fast Charge SilTerra 0.18um
Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.
查看 Compact, efficient 64-bit RISC-V processor with 5-stage pipeline 详细介绍:
- 查看 Compact, efficient 64-bit RISC-V processor with 5-stage pipeline 完整数据手册
- 联系 Compact, efficient 64-bit RISC-V processor with 5-stage pipeline 供应商
Block Diagram of the Compact, efficient 64-bit RISC-V processor with 5-stage pipeline

RISC-V IP
- TESIC CC EAL5+ Secure Element IP Core
- Intelligent Sensor and Power Management Design Platform
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- RISC-V processor - 32 bit, 5-stage pipeline
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers