AV1/HEVC/AVC/VP9 Dual-core Video Codec HW IP: 8K60fps/4K240fps in Real-time
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CML I/O Pad Set
The CML library provides a differential current mode logic clock driver to support REFCLK signaling in PCIe applications along with a CML voltage reference cell. Also included is a full complement of power and spacer cells to assemble a CML domain in the pad ring by abutment.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in an inline CUP wire bond implementation with a flip chip option.
When using this library with GPIO and other I/O libraries provided by Aragio Solutions, a rail splitter is required to isolate the CML driver in its own power domain. That rail splitter can be obtained from the 1.8V Support: Power library.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in an inline CUP wire bond implementation with a flip chip option.
When using this library with GPIO and other I/O libraries provided by Aragio Solutions, a rail splitter is required to isolate the CML driver in its own power domain. That rail splitter can be obtained from the 1.8V Support: Power library.
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