The CML library provides a differential current mode logic clock driver to support REFCLK signaling in PCIe applications along with a CML voltage reference cell. Also included is a full complement of power and spacer cells to assemble a CML domain in the pad ring by abutment.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in an inline CUP wire bond implementation with a flip chip option.
When using this library with GPIO and other I/O libraries provided by Aragio Solutions, a rail splitter is required to isolate the CML driver in its own power domain. That rail splitter can be obtained from the 1.8V Support: Power library.
- CML Differential Clock Driver Features:
- ▪ Differential current-mode-logic clock driver with very low jitter
- ▪ Target application – PCIe 100 MHz REFCLK
- ▪ Typical differential input voltage swing – 0 to 400 mV (referenced to ground)
- ▪ Jitter < 3ps @ 100 MHz with ±100 mV power supply ripple noise
- ▪ Common mode voltage (VOS) = 380mV @ 1.5V and 400mV @ 1.8V
- ▪ Output-disable and power-down modes
- ▪ Powered by 1.5V / 1.8V I/O and 0.8V Core supplies
- ▪ Power-up sequencing independent design with Power-On-Control
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)