Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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Bi-Directional LVDS with LVCMOS
BiDirectional LVDS IO circuit combines LVDS driver and receiver circuits to enable a single pair of IO pads to function as a 1.5Gbps bi-directional LVDS driver and receiver. Both driver and receiver circuits can be independently enabled (allowing driver, receiver, or loopback functions). If both driver and receiver circuits are disabled the IO pads function as independent single-ended LVCMOS IOs. The circuit has low area and power and operates o of standard IO and core supply voltages.
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Block Diagram of the Bi-Directional LVDS with LVCMOS
LVDS IP
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane