The BFP IQ compression IP core is a silicon agnostic implementation of a lossy Block Floating Point compression and de-compression scheme that improves fronthaul bandwidth efficiency.
The IP has been designed to conform with the O-RAN CUS-plane protocol standard v2.0 but can also be used in any arbitrary system where fronthaul bandwidth is a limiting factor. The IP core enables quick and reliable deployment of compression and de-compression at both radio and baseband side and can be configured to handle any kind of fronthaul implementation.
The core can either be used in a 5G/4G radio mode where compression is made on larger blocks, e.g. Resource Blocks, or as a single unit that performs compression on a sample by sample basis.
- Delivering Performance
- Compression from 24-bit fixed point IQ to 8-15 bit mantissa + 4 bit exponent
- Configurable block size for compression Very low micro-second latency
- Very small silicon footprint
- Few clock cycles processing latency
- Easy to use
- Matlab evaluation scripts can be provided
- Easy to configure
- Standard streaming interface for input/output
- Silicon Agnostic
- Implemented in synthesizable SystemVerilog and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
- Enables lower capacity backhaul like microwave links
- Improves throughput on existing microwave links
- Enables reduction of fiber connections between radio site and baseband site
- IP core: RTL is delivered as source code (encrypted or un-encrypted System Verilog) or netlist
- User Manual: Describing among others top Level I/O’s definition, registers, clocking strategy, functional description
- Test cases: Delivered with System Verilog UVM
- Connecting RU with BU
- Chip-to-chip RU systems
- Test Systems
Block Diagram of the BFP IQ Compression and De-compression