You are here:
Emulation of RF and channel impairments in Verilog
The BAY9 Virtual RF (VRF) is an IP core written in Verilog, that allows to emulate most system aspects of a typical RF transmission. When connected to a physical layer (PHY) core, the VRF IP core replaces a real RF device between TX-DAC output and RX-ADC input.
特色
- DAC emulation - request p samples every q clock cycles
- IQ imbalance + DC offset
- PA amplitude compression and phase shift
- FIR type fading channel
- Frequency + sampling clock offset
- Additive White Gaussian Noise
- RX gain control with arbitrary definition of attenuation, pin setting, and delay
- Available as Verilog source code without vendor specific IP cores
优势
- Test and verify PHY implementations in real time
- Optimize parameters
- Create BER/FER curves in a fast and reproducible way
- Avoid the effort to connect a real RF
可交付内容
- Verilog source code
- Matlab/Octave control functions
- Documentation
查看 Emulation of RF and channel impairments in Verilog 详细介绍：
- 查看 Emulation of RF and channel impairments in Verilog 完整数据手册
- 联系 Emulation of RF and channel impairments in Verilog 供应商
Virtual RF
- Bluetooth controller for connectivity with low-power consumption for extended battery life
- Bluetooth 5 controller for secure connectivity with low-power consumption for extended battery life
- Bluetooth, Thread, and Zigbee controller for secure and concurrent wireless connectivity with low-power consumption
- Intelligent Sensor and Power Management Design Platform
- IEEE 802.11 ah WiFi HaLow