Emulation of RF and channel impairments in Verilog

特色

• DAC emulation - request p samples every q clock cycles
• IQ imbalance + DC offset
• PA amplitude compression and phase shift
• FIR type fading channel
• Frequency + sampling clock offset
• Additive White Gaussian Noise
• RX gain control with arbitrary definition of attenuation, pin setting, and delay
• Available as Verilog source code without vendor specific IP cores

优势

• Test and verify PHY implementations in real time
• Optimize parameters
• Create BER/FER curves in a fast and reproducible way
• Avoid the effort to connect a real RF

可交付内容

• Verilog source code
• Matlab/Octave control functions
• Documentation

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