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Baseline and Extended JPEG Encoder Core
This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, ASIC or FPGA hardware JPEG encoder with very low pro-cessing latency.
The JPEG-EX-S Encoder produces compressed JPEG images and the video payload for Motion JPEG container formats. It accepts images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it requires just 80,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use encoder requires no assistance from a host pro-cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.
Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its delivera-bles include a complete verification environment and a bit-accurate software model.
The JPEG-EX-S Encoder produces compressed JPEG images and the video payload for Motion JPEG container formats. It accepts images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.
The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it requires just 80,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use encoder requires no assistance from a host pro-cessor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.
Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its delivera-bles include a complete verification environment and a bit-accurate software model.
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Block Diagram of the Baseline and Extended JPEG Encoder Core
Baseline and Extended JPEG Encoder Core IP
- Ultra-Fast Baseline and Extended JPEG Encoder Core
- 10/12-bit Extended & 8-bit Baseline JPEG Encoder with optional Constant Bitrate Motion JPEG Video Rate Control
- Ultra-Fast Baseline and Extended JPEG Decoder Core
- High Performance 8bit/12bit JPEG CODEC
- Baseline and Extended JPEG Decoder Core
- Baseline and Extended JPEG Decoder Core