The AXI Virtual controller is provided under the terms of the XILINX End User License and is included with ISE® and Vivado™ design tools at no additional charge.
Xilinx provides the AXI Virtual FIFO Controller core to use external DRAM memory as multiple FIFO blocks.
The AXI Virtual FIFO Controller is a key Interconnect Infrastructure IP which enables users to access external memory segments as multiple FIFO blocks. The AXI Virtual Controller provides AMBA® AXI4-Stream write (master) as well as read (slave) interface to AXI4 DRAM memory mapped interface of external memory.
- Configurable multiple FIFO interfaces (up to 8) channels.
- FIFO FIFO full and empty check per channel
- Supports data width of 32, 64, 128, 256, 512 and 1024.
- Supports AXI4 memory mapped burst of 512, 1024, 2048 and 4096 bytes