Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
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AXI Protocol Checker
The AXI Protocol Checker core is designed to monitor AXI interfaces. When attached to an interface, it actively checks for protocol violations and provides an indication of which violation occurred.
The checks are synthesizable versions of the System Verilog protocol assertions provided by ARM in the “AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertion” library.
The checks are synthesizable versions of the System Verilog protocol assertions provided by ARM in the “AMBA 4 AXI4, AXI4-Lite, and AXI4-Stream Protocol Assertion” library.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC