APB Subsystem

The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem is ready for integration with processors having either an AHB or an AXI interface such as the BA2x processors, and several ARM Cortex and RISC-V processors. The peripherals connect to the 32-bit APB ports of the APB bridge, which allows configuring the base address and the size of the address space for each peripheral. The subsystem includes the following modules:
- I2C Master & Slave
- Single/Dual/Quad/Octal SPI Master & Slave
- 16550-compatible UART
- 32 GPIOs
- Real-Time Clock
- Watchdog Timer
- Generic Timer
- Programmable Interrupt Controller

Other peripherals with a 32-bit APB interface can be connected to the subsystem, via a configurable number of extra 32-bit APB ports. Each of the extra APB ports are configured independently to comply to APB2, APB3 or APB4 standard. The included bridge allows connecting the subsystem to a 32-bit or 64-bit AHB or AXI bus.

The APB-SBS was designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. It is delivered in human-readable Verilog source code along with comprehensive documentation for each module, example drivers, and software exercising all the peripherals.

This subsystem can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.

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