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High performance hstl transceiver IP Listing

192 IP Cores (81 - 120)

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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process

TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock ...

81
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process

TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock ...

82
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process

TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock ...

83
TSMC 40nm 和 SMIC 55nm 中的蓝牙 LE v5.3 / IEEE 15.4 RF IP（经过硅验证的 IP）

这个射频收发器IP和调制解调器IP已经在55nm ULP、40nm ULP、FLASH process nodes得到验证。这一组设计符合Bluetooth Low Energy v5.3和IEEE 802.15.4（ZigBee 3）的规范要求。最高...

84
USB 2.0 PHY IP，在 UMC 28HPC 中经过硅验证

USB2.0 PHY IP是完整的物理层（PHY）IP解决方案，具有卓越的性能和低功耗模式。这个USB 2.0高速收发器，可与主机、设备或OTG功能控制器一起使用。USB2.0 PHY IP遵循UTMI+ 3级规范...

85
USB 2.0 Device IP Core

A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface. The USB 2.0 Device IP Core is ideal for applications ...

86
802.15.4 (Zigbee, 6LoWPAN, RF4CE, ISM) PHY

The 802.15.4 Transceiver core supports the PHY layer for a range of wireless PAN standards including Zigbee®, 6LoWPAN, RF4CE and other ISM band applications. The IQ architecture integrates ...

87
Interlaken, 100G, 12 Lanes

Altera's Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet, and data center applications that demand high IP configurability to optimize for system ...

88
Interlaken, 100G, 20 Lanes

Altera's Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet, and data center applications that demand high IP configurability to optimize for system ...

89
Interlaken, 40G, 8 Lanes

Altera's Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet, and data center applications that demand high IP configurability to optimize for system ...

90
2.4GHz+Sub-GHz 802.15.4g+802.11ah for SUN

SBR6201 is a fully integrated dual-band transceiver IP for 802.15.4g and 802.11ah applications. It is optimized to deliver superior performance for Smart Utility Network (SUN) applications. ...

91
25G PHY in TSMC (16nm, 12nm, N7, N6)

The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY ...

92
PCIe 2.0 PHY in Fujitsu (40nm)

The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY provides a cost-effective ...

93
PCIe 2.0 PHY in SMIC (40nm, 28nm)

The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for higher bandwidth. The PHY provides a cost-effective ...

94
USB 2.0 Device Controller

The USB 2.0 Device Controller IP Core is an USB 2.0 compliant device core with optional PCI, Custom, or AHB master/slave interfaces. The USB 2.0 device core supports 480 Mbit/s in High Speed ...

95
BLE 4.2 SoC White Box IP

The BLE 4.2 SoC White Box IP solution is the design data base of a fully compliant BLE 4.2 production chip with SW and profiles including Mesh and Audio profiles allowing easy connectivity with ...

96
1.25 Gbps EPON SerDes IP

The MXL-SRDS-EPON is an Ethernet Passive Optical Network (EPON) transceiver implemented in digital CMOS technology. The SerDes IP offers data transfer rate of 1.25Gbps, for both upstream & downstream ...

97
Dual WideBand Frequency Synthesizer with Integrated VCO and Loop Filter

CorePLL is a wideband phase-locked loop (PLL) system for 2G (GSM) 3G and 4G (LTE), including Carrier Aggregation (CA) for 3GPP Rel11 and Rel12. CorePLL frequency synthesis sub-system enables ...

98
Bluetooth Low Energy (BLE) analog PHY

B55NLL_BLE_PMU PHY provides complete Bluetooth Low Energy (BLE) analog PHY. The RF is a high performance 2.4GHz ISM band wireless transceiver. It integrates both high sensitivity receivers and ...

99
SATA 3.0 PHY

The INNOSILICON mixed signal SATA3.0 transceiver PHY provides a complete SATA3.0 standard compliant transceiver physical interface solution for delivering high speed data over point to point ...

100
10 Gb/s full HW stack UDP/IP Transmitter/Receiver

10 Gb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based systems In application areas such as Data Communication and Imaging, ...

101
10/100 Ethernet PHY, TSMC 28nm HPC+

-10 100ETHERNET-T28HPCP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream to and from a Media Access Control (MAC) ...

102
物联网(IoT)平台

Cortus 物联网(IoT)平台只需极少的外部组件，即能拥有各种高级功能。广泛的接口选项和超低功耗的表现使其成为物联网的理想解决方案。其核心是高性能且低功耗的无线电收发器，...

103
USB 2.0 Human Interface Devices Design Platform

The USB 2.0 HID Design Platform is a complete, integrated solution dedicated to wide range of USB based Human Interface Devices like mouse, keyboard or pen tablet. The complete HID Design ...

104
USB 2.0 Mass Storage Devices Design Platform

The USB 2.0 Mass Storage Design Platform is a complete, integrated solution dedicated to wide range of USB based Mass Storage Devices. You can use it in wide range of applications, like portable ...

105
USB 2.0 Audio Devices Design Platform

The USB 2.0 Audio Design Platform is a complete, integrated solution, dedicated for USB based Audio Devices, like microphone and speakers. DCD’s Audio Design Platform includes: - DUSB2 ...

106
Serial ATA Bridge Controller (1.5, 3.0, 6.0 Gb/s)

The Serial ATA Bridge IP Core provides an method to manipulate data between two SATA endpoints. High Performance, with maximum bandwidth data transfers.

107
10/100/1000 Ethernet (Triple Speed)

As the leading provider of 1 Gbps Ethernet (GbE) for FPGA and HardCopy® ASIC devices, Altera offers the Triple-Speed Ethernet MegaCore® function, allowing you to easily build systems with ...

108
Aurora 64B/66B

Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA Aurora is a LogiCORE™ IP designed to enable easy implementation of Xilinx transceivers while ...

109
Aurora 8B/10B

Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA. Aurora is a LogiCORE IP designed to enable easy implementation of Xilinx transceivers while ...

110
Serial RapidIO Controller

The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2. So_ip_srio_ctrl soft core is fully compliant with the RapidIO 2.2 ...

111
Serial FPDP

Serial Front Panel Data Port is an industry standard, low-overhead, low-latency, high speed serial communications protocol. sFPDP is ideal for use in applications such as high-speed communication ...

112
100-Gbps Ethernet MAC & PHY

Altera offers the 40 Gbps Ethernet (40GbE) and 100 Gbps Ethernet (100GbE) MegaCore® function intellectual property (IP) cores for building systems with very high throughput-rate standard Ethernet ...

113
10GBase-KR PHY

Altera provides a complete 10 Gbps Ethernet over backplane 10GBASE-KR physical coding sublayer (PCS), and physical media attachment (PMA) sublayer intellectual property (IP) known as PHY IP. ...

114
40-Gbps Ethernet MAC & PHY

Altera offers the 40 Gbps Ethernet (40GbE) and 100 Gbps Ethernet (100GbE) MegaCore® function intellectual property (IP) cores for building systems with very high throughput-rate standard Ethernet ...

115
SerialLite III Streaming

Altera?s SerialLite III MegaCore® function intellectual property (IP) continues to scale with today's demand for more bandwidth and higher performance needs. SerialLite III is a simple, low ...

116
Triple Speed Ethernet with 1588

As the leading provider of 1 Gbps Ethernet (GbE) for FPGA and HardCopy® ASIC devices, Altera offers the Triple-Speed Ethernet MegaCore® function, allowing you to easily build systems with ...

117
Adaptive Modem from 4-QAM to 1024-QAM "Manero"

The Binary Core coded modulation scheme bc005 ("Manero") is extremely compact, highly modular, and it supports all square and cross modulation formats from 4- up to 1024-QAM. The modem is well ...

118
Xilinx HMC Controller

The Xilinx® LogiCORE™ IP HMC Controller implements a high performance, configurable HMC host controller for user to interconnect with external HMC (Hybrid Memory Cube) devices. The core ...

119
Serial Front Panel Data Port Gen3

Serial Front Panel Data Port Gen3 is a next-generation, high bandwidth serial communications protocol defined by the ANSI/VITA 17.3-2018 standard. sFPDP-Gen3 supports single-lane or multi-lane ...

120

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