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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling needs. It has features like clocking and clock & data recovery, Serialization and De-Serialization of Data, 8/10b data coding, Receiver detection.
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 55nm LP process.
* A limited number of Test Chips manufactured in TSMC 55LP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
TERMINUS CIRCUITS’s USB 3.1 PHY uses 32/16bit Data PIPE interface. It also supports lower power management’s states like P0s, P1, P1-sub-states and P2. USB 3.1 PHY IP is available in TSMC 55nm LP process.
* A limited number of Test Chips manufactured in TSMC 55LP (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.
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USB GEN1 IP
- USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
- Multi-Link Multi-Protocol SerDes - USB 3.1 PHY IP Gen1 TSMC 16FF+LL
- Multi-Link Multi-Protocol SerDes - USB 3.1 PHY IP Gen1 TSMC 16FF+GL
- USB3.2 Gen2 Device Controller IP Core
- USB3.0 DR-OTG Controller IP Core
- Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process