MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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800MHz Low Jitter PLL
The ll_pll2661s01_ln28lpp_7000 is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis. It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 9-bit main-divider, and an automatic frequency control (AFC).
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Block Diagram of the 800MHz Low Jitter PLL
Low Jitter PLL IP
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