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8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA
The SiFive Performance P270 is an 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA. With full support for the RISC V Vector Extension v 1.0RC, and combined with the SiFive Recode utility, which translates existing SIMD software from popular legacy architectures to RISC-V Vector assembly code, the P270 is an ideal replacement for dated SIMD architectures.
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Block Diagram of the 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA
CPU IP
- High Bandwidth Out-of-Order RISC-V CPU IP Core
- All in one solution for AI in RISC-V
- 2D (vector graphics) GPU IP Further advanced architecture for minimized CPU load and increased pixel performance in vector processing
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load
- High Bandwidth In-Order RISC-V CPU IP Core
- RISC-V Processor - RV12 - 32/64 bit, Single Core CPU