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640 MHz Low Jitter PLL (71107)
It is a dual supply voltage integer low jitter Phase Locked Loop (PLL). It generates an 640MHz output clock with jitter of 2ps, RMS. The input clock bypass mode and glitch-free post-diving function are available.
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Block Diagram of the 640 MHz Low Jitter PLL (71107)
low jitter pll IP
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