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640 MHz Low Jitter PLL (71107)
It is a dual supply voltage integer low jitter Phase Locked Loop (PLL). It generates an 640MHz output clock with jitter of 2ps, RMS. The input clock bypass mode and glitch-free post-diving function are available.
特色
- 14nm Low Power CMOS device technology
- 1.8V, 0.9V to 0.8V dual power supply
- Operation junction temperature: -40 to 125°C
- Input frequency : 40MHz (fixed frequency)
- Output frequency : 640MHz (fixed frequency)
- Integrated RMS jitter: 2ps(integrated from 50kHz to 80MHz)
- Output clock duty ratio: 48 to 52%
可交付内容
- Data Sheet
- User Guide
- Verilog model
- Timing LIB
- CDL netlist
- Layout (GDSII or OAS)
应用
- Mobile/Consumer/IoT
Block Diagram of the 640 MHz Low Jitter PLL (71107)
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