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64-bit RISC-V Single Core Microprocessor
VEGA AS1061 features an in-order processing engine with a 6 stage pipeline enabling it to meet high-performance embedded application requirements. The processor also supports single and double precision floating point instructions, and MMU for Linux based applications. AS1061 is optimized for high performance with integrated Instruction Cache, Data Cache and an advanced branch predictor enabling efficient branch execution. Features also include PLIC and vectored interrupts for serving various types of system events. An AXI or AHB interface enables ease of system integration and JTAG debug interface for development support.
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Block Diagram of the 64-bit RISC-V Single Core Microprocessor
Video Demo of the 64-bit RISC-V Single Core Microprocessor
VEGA Processor Introduction
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- 32-bit Embedded RISC-V Functional Safety Processor
- 64-bit RISC-V Application Processor Core
- Dual-issue Linux-capable RISC-V core