MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
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64-bit RISC-V embedded core with in-order single issue pipeline
64-bit RISC-V embedded core with in-order single issue pipeline.
Optimized for low power and small area. Perfectly fits for embedded control.
Optimized for low power and small area. Perfectly fits for embedded control.
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Block Diagram of the 64-bit RISC-V embedded core with in-order single issue pipeline
64-bit Processor IP
- 64-bit RISC-V Multi-Core Linux-Capable processor
- Ultra High Performance 64-bit RISC-V Embedded Processor
- High Performance 64-bit RISC-V Multi-Core Application Processor
- 64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN
- 64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
- 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension