PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
56G SerDes
The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics and backplanes with the built-in low-jitter LC PLL and CDR to optimize the signal integrity. The Innosilicon 56G Long Reach Serdes solution meets the functionality, power, performance and area requirements of a variety of network applications.
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