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50MHz to 800MHz Integer-N Phase-Locked Loop
055TSMC_PLL_03 is a PLL frequency synthesizer that generates two clock signals in the range from 1 MHz to 50MHz. The synthesizer consists of one voltage-controlled oscillator (VCO) with internal LC circuit and automatic subband selection system; a digital phase frequency detector (PFD); a precision charge pump (CP) with integrated adjustable loop filter; a programmable divider of reference signal; a system of programmable feedback dividers controlled by a delta-sigma modulator (DSM) and output signal dividers.
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