50MHz to 800MHz Integer-N Phase-Locked Loop

065TSMC_PLL_10 is a integer-N synthesizer, which forms clock signal with frequency from 50 MHz to 800 MHz. It consists of the ring VCO with frequency from 400 MHz to 800 MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency. Output frequency is calculated by formula: FLO = (Fref*N)/(R*C). Output signal is CMOS compatible.

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