32G Multi-protocol SerDes PHY

特色

• Multi-protocol PHYs supporting data rate in the range of 2.5 Gbps – 32 Gbps
• Available in GLOBALFOUNDRIES 22FDX® process node
• Optimized for low-power operation and north/south die-edge placement
• AC-coupled RX front end with on-chip capacitors
• Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
• Duplex Lane configurations of x4 and x1
• LC-PLLs provide a wide range of operating frequencies
• Wide range programmable multipliers for reference clock multiplication
• Differential reference clock inputs are selectively sourced from C4 or internal ASIC interface pins
• Flexible ASIC clocking
• Programmable clock outputs from the PLL to the ASIC core
• Parallel data, transmitted to the PMA, is synchronous to the transmit parallel data clock from the ASIC core
• Tight lane skew control in the PMA
• Adaptive receive equalizer with programmable CTLE and DFE support
• Support transmit FIR adaptation through back channel for Ethernet applications
• Built-in Self Test (BIST) support
• At-speed functional test capability with low-speed reference clocks
• Built-in PRBS15/31 and custom pattern generation and checking for standalone testing
• Internal serial loopback with optional phase advancing
• Parallel loopback supported within the PMA
• In-situ real-time monitoring and receive data eye schmoo through an adaptive receive sampler
• ATPG Mux Scan support for digital logic
• IEEE 1149.6 JTAG boundary scan for serial link pins
• Multiple interfaces for the access of PMA registers
• Provides direct register control of all PMA functionality, as well as extended features
• Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
• Optional MDIO interface can be provided as required for Ethernet standard PHYs
• PHYs are spec compliant across a wide operating junction temperature range (-20 °C to 125 °C). PLLs, bias circuits, and data path are functional between -40 °C to -20 °C

优势

• Duplex lane configurations of x2, x4, and x8
• Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mV for SR
• Support for AC-coupled interfaces
• Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
• BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and GbE protocols
• A wide range of PLL multiplication supporting low reference clock frequencies
• Flexible ASIC clocking
• Tight skew control of 2UI between lanes of the PMA
• 3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
• Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
• 8-tap Rx DFE (Decision Feedback Equalizer)
• Second-order CDR meeting SSC and RX sinusoidal jitter requirements
• Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
• Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
• Built-in PRBS pattern generation and checking for standalone loopback testing
• In-situ real-time monitoring and receive data eye schmoo
• Operation across a wide temperature range (-40 C to +125 C)

可交付内容

• PMA Hard Macro and Design Kit
• Verilog models
• LEF abstracts (.lef)
• Timing models (.lib)
• CDL netlists (.cdl)
• ATPG scan and IEEE 1149.6 AC boundary scan
• IBIS-AMI models
• GDSII layout
• DRC & LVS reports
• Datasheet
• SoC Integration guide
• Optional design integration and bring-up support services

Block Diagram of the 32G Multi-protocol SerDes PHY

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