64G/56G SerDes
The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics and backplanes with the built-in low-jitter LC PLL and CDR to optimize the signal integrity. The Innosilicon 56G Long Reach Serdes solution meets the functionality, power, performance and area requirements of a variety of network applications.
The PHY is fully compliant with the following standards: PCIE6/5, IEEE 802.3 and OIF, CEI-56G+ LR PAM-4, CEI-25G+ LR/MR NRZ, JESD204C/B (25/32G), 10GKR/100G KR-4 LR, 400GAUI-8 LR/MR, CEI11G-LR.
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65G/56G SerDes IP
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- Programmable Low Power V-by-One SERDES - GLOBALFOUNDRIES 65 65G
- 56G SerDes Ethernet
- 28Gbps MR SerDes IP on TSMC 28nm