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32-bit Application Processor
The BA25 is a 32-bit processor for demanding systems running applications on general-purpose operating systems such as Linux and Android. The high-performance BA25 processor runs at high clock frequencies yet has a smaller silicon footprint than most competing application processors (e.g., over 1100MHz and from 145k sq. um in TSMC 28nm HPM, including the FPU, and excluding SRAMs).
This royalty-free 32-bit processor core is binary-compatible with other members of the silicon-proven BA2x processor family. Its BA2 instruction set is relatively simple and extremely compact, offering system area and energy savings benefits. Programing is facilitated with the included C/C++ tool chain, Eclipse IDE, architectural simulator, and ported C libraries, RTOSs, and OSs.
The seven-stage pipelined architecture runs at high frequencies and further enhances performance by supporting out-of-order execution and branch prediction. An optional IEEE 754 compliant floating-point unit accelerates floating point computations.
The BA25 processor uses two-level data and instruction caches—with L0 running at the CPU’s clock frequency and L1 running at half that—and a two-level memory management unit. The size and associativity of the caches and MMU are configurable at synthesis time. The system interface uses two AMBA® AXI4™ buses, one for data and one for instructions, both of configurable data width. Two tightly-coupled quick memory (QMEM) buses allow fast access for time-critical code and data, and can be used for inter-core communication in a multi-core architecture.
The energy efficiency BA25 enables power management with clock gating and power shut-off of unused units, and through software and hardware control over the clock frequency of the CPU and buses. Wake-up from sleep mode is triggered by an interrupt issued by the embedded tick-timer or by an external source.
This royalty-free 32-bit processor core is binary-compatible with other members of the silicon-proven BA2x processor family. Its BA2 instruction set is relatively simple and extremely compact, offering system area and energy savings benefits. Programing is facilitated with the included C/C++ tool chain, Eclipse IDE, architectural simulator, and ported C libraries, RTOSs, and OSs.
The seven-stage pipelined architecture runs at high frequencies and further enhances performance by supporting out-of-order execution and branch prediction. An optional IEEE 754 compliant floating-point unit accelerates floating point computations.
The BA25 processor uses two-level data and instruction caches—with L0 running at the CPU’s clock frequency and L1 running at half that—and a two-level memory management unit. The size and associativity of the caches and MMU are configurable at synthesis time. The system interface uses two AMBA® AXI4™ buses, one for data and one for instructions, both of configurable data width. Two tightly-coupled quick memory (QMEM) buses allow fast access for time-critical code and data, and can be used for inter-core communication in a multi-core architecture.
The energy efficiency BA25 enables power management with clock gating and power shut-off of unused units, and through software and hardware control over the clock frequency of the CPU and buses. Wake-up from sleep mode is triggered by an interrupt issued by the embedded tick-timer or by an external source.
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Block Diagram of the 32-bit Application Processor
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