The circuit is 2-bit ADC with programmable threshold. Least significant bit, calling sign bit, turns to 1 or 0 with changing of differential input signal polarity. Most significant bit, calling magnitude bit, turns to 1 if there is an excess of the threshold by differential input signal.
The block consists of reference voltages and currents generator, 2 voltage followers, 2 ADCs (for each channel) and multiplexers of input signal.
Thresholds are choosed by external 4-bit binary code in range from 60 mV to 220 mV. Threshold’s step equals 10 mV. There are two modes to define the threshold: «12 levels» mode and «16 levels» mode. Shifting between these modes is adjusted by logical level at lvl_12_mode input: logical “1” for «12 levels» mode; logical “0” for «16 levels» mode. There is a possibility to adjust the dc level of thresholds’ scale within 10 mV, wherein quantizing step remains unchangeable. Scale adjustment implemented by binary code at input scale_adj. Scale adjustment affects both channels at the same time.
There is logical error detector in ADC. In case of appearance one of faulty decisions logical level at the error output of corresponding channel. The faulty decisions are:
- Simultaneous signal of negative sign and upper threshold crossing
- Simultaneous signal of positive sign and lower threshold crossing
- Simultaneous signal of both upper and lower thresholds crossing
- UMC CMOS 180 nm
- Resolution 2-bit
- Adjustment of threshold levels
- Adjustment of dc level of thresholds scale
- Analog supply voltage – 3.3 V; digital supply voltage – 1.8 V
- Supported foundries: TSMC, Global Foundries, SMIC, iHP, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Special processors in navigation systems
- AGS systems