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2/64/128 CMOS/ECL PLL high-frequency divider

The CMOS high-frequency divider consists of two independent circuits. The first divider is a set of serially connected CMOS dividers with a dividing ratio 2. The second circuit is based on ECL logic and has differential signal. The reference current source of ECL circuit has temperature dependent and temperature independent modes. The buffer-commutators are used to output the signal of a frequency divided by 2, 64 or 128.
The block is fabricated on TCMS BiCMOS 0.18 um technology.

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2/64/128 CMOS/ECL PLL high-frequency divider

查看 2/64/128 CMOS/ECL PLL high-frequency divider 详细介绍：

PLL divider IP

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