The S3DA424M12BT40LP employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are
minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency, 212MHz.
- 40nm TSMC LP Process, 6 Metals Used (No Analog Options)
- 3.3V and 1.1V Supplies
- Sampling Rate up to 450MS/s
- 1.0Vpp Differential Output Range
- Programmable full-scale current possible 4-20mA
- Performance for Fout<90MHz, SFDR > 62dBc,ENOB>10.0bits
- MTPR 57dB up to 90MHz @ PAPR=17dB
- MTPR 52 dB, up to 212MHz @ PAPR=17dB
- Stand-By and Power-Down Modes
- Compact Die Core Area: 0.20mm2
- The 12-bit DAC dynamic performance highlights considering a signal frequency of 10MHz and 450MS/s conversion rate include an SNDR > 66dB and an SFDR > 62dBc.
- The S3DA424M12BT40LP is designed in a 40nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (verilog)
- Integration Support
- Next Generation DSL
- Wireline Communications
- Wireless Communications Infrastructure
Block Diagram of the 12Bit 424M采样率DAC，用于电力线通信/下一代DSL/无线通信