The S3DA400M12BTJ18 employs a current steering architecture with differential current outputs. It uses 7 linear bits and 5 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit DAC features an excellent static performance that includes ±0.5LSB DNL and ±1LSB INL. Dynamic performance highlights considering a signal frequency with 10MHz and 400MS/s conversion rate include an SNDR of 67dB and an SFDR of 75dBc.
The S3DA400M12BTJ18 is designed in a 180nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- TowerJazz 0.18μm TS18 Standard Logic Process
- 3.3V and 1.8V Supplies
- Sampling Rate up to 400MS/s
- 1.0Vpp Differential Output Range
- DNL< 0.5LSB Typ.; INL< 1LSB Typ.
- 20mA Output current
- High Performance at 400MS/s
- SNDR = 67dB, SFDR = 75dBc, Fout= 10MHz
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
- DVB-C, DOCSIS
- WiFi 802.11X, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 400MS/s Current Steering DAC