The S3DAIQ320M12BSS28LPP employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
- 28nm Samsung LPP Process, 7 Metals Used
- 1.8V and 1.0V Supplies
- Sampling Rate up to 320MS/s
- 1.0Vpp Differential Output Range
- DNL< 1.0LSB; INL<2.0LSB.
- High Performance for Fout<40MHz
- SNR > 68dB, SFDR > 62dB,ENOB>10bits
- In-band SFDR=74dB with Fout=40MHz
- IM3>-69dBc @40MHz
- Stand-By and Power-Down Modes
- Die Area post-shrink: 0.187mm2
- This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture and randomization of the output current sources.
- The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
- DVB-C, DOCSIS 3.0
- WiFi 802.11xx, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 320MS/s Dual Current Steering DAC