12-Bit 100MHz Current Steering DAC

特色

• 40nm TSMC Logic LP Process, 6 Metals Used
• 2.5V and 1.1V Supplies
• Sampling Rate up to 100MS/s
• Programmable Voltage or Current Output
• 1.5Vpp Differential Output Range
• 8mW Power Dissipation at 2.5mA output current
• DNL< 1LSB Typ.; INL< 1.5LSB.
• High Performance at 100MHz clock rate
• SNR = 68dB, SFDR = 70dB, Fout= 12MHz
• Stand-By and Power-Down Modes
• Compact Die Area: 0.1mm2

优势

• This 12-bit DAC features an excellent static performance that includes ±1LSB DNL and ±1.5LSB INL.
• Dynamic performance highlights considering a signal frequency with 12MHz and 100MHz conversion rate include an SNR of 68dB and an SFDR of 70dBc.
• The S3DA100M12BT40LPA is designed in a 40nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
• The DAC block support either current or voltage output. The voltage output are generated by a set of internal reference resistors which generate a maximum 2.0Vpk-pk differential output swing signal.

可交付内容

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (.lib)
• Behavioral Model (Verilog)
• Integration Support

应用

• WiFi 802.11X, WiMAX 802.16x
• LTE, GSM
• Wireline communications
• Envelope Tracking

Block Diagram of the 12-Bit 100MHz Current Steering DAC

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