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112G XSR Multi-protocol SerDes PHY

A high-bandwidth, ultra-low power SerDes PHY solution for extremely short reach (XSR) 112G inter-die connections in system in package (SiP) devices serving next-generation networking and hyperscale data center applications.

The Rambus 112G XSR Multi-Protocol SerDes (MPS) PHY is a comprehensive IP solution designed to provide best-in-class performance for the high-bandwidth connections between die or chiplets in SiP devices. The 112G MPS PHY supports PAM-4 and NRZ signaling and data rates from 25 to 112 Gbps. It is tailored for the ultra-low power and area requirements of die-to-die interfaces.

The 112G XSR MPS PHY is designed with a system-oriented approach, maximizing flexibility in today’s most challenging system environments including specifically:

Die-to-die (D2D) interfaces
Die-to-optical engine (D2OE) interfaces

Available in advanced 7nm FinFET process.

特色

Supports up to 8 duplex lanes and data rates from 25 to 112 Gbps
Ultra-low power configurable architecture for D2D and D2OE interfaces
Design flexibility allows for placement along all ASIC edges in an ASIC
Programmable TX/RX equalizers including: Multi-tap digital FFE and CTLE
A centralized LC-PLL supports a wide range of reference clock frequencies and lane operating frequencies
PMA is spec. compliant across a wide operating junction temperature range (-20 °C to 105 °C). PLLs, bias circuits, and data paths are functional between -40 °C to 125 °C
In-situ real-time monitoring and receive data eye voltage histogram
Built in PRBS generators and checkers along with custom pattern generation
ATPG Mux Scan support for digital logic
IEEE 1149.6 JTAG boundary scan for SerDes pins
Built-in BER monitor including a 40-bit counter to count the total number of bits received and a 30-bit counter to count the total number of errors detected by a pattern checker
Internal serial loopback and parallel loopback support
Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
Analog and digital test bus

优势

Duplex lane configurations of x2, x4, and x8
Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mV for SR
Support for AC-coupled interfaces
Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
BER of 10-15 for CEI11-LR/SR and BER of 10-12 for SFI, XFI, PCIe and GbE protocols
A wide range of PLL multiplication supporting low reference clock frequencies
Flexible ASIC clocking
Tight skew control of 2UI between lanes of the PMA
3-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
8-tap Rx DFE (Decision Feedback Equalizer)
Second-order CDR meeting SSC and RX sinusoidal jitter requirements
Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
Built-in PRBS pattern generation and checking for standalone loopback testing
In-situ real-time monitoring and receive data eye schmoo
Operation across a wide temperature range (-40 C to +125 C)