This dual channel ADC accepts an input clock of up to 120Mhz, depending on required bandwidth. It uses the 2 ADC cores with shared references and timing, to ensure excellent phase and gain matching performance.
The ADC has differential inputs in order to maximize dynamic range and noise immunity. The ADC is preceded by a bypassable integrated buffer which allows the ADC to accept an input signal amplitude of 1Vpk-pk.The exclusion of this buffer limits the ADC to an input range of 0.5Vpk-pk but offers better power performance.
The ADCï¿½s power is scalable with sample frequency.